Register map

ASIM team
LIP6 Laboratory
Paris, France

Next: Device and Vendor Identification Up: Configuration registers Previous: Register access modes

Register map

This map describes the register space. The first one concerns the standard registers. Few registers are unused since PCI-DDC contains neither RAM nor ROM nor even PCMCIA device. Thus, only the arrow right tagged registers are used and therefore described below.

&31&&&&&&&24&23&&&&&&&16&15&&&&&&&8&7&&&&&&&0&

00h16Device ID 16Vendor ID &  p.
04h16Status 16Command &  p.
08h8Base Class Code 8Sub Class Code 8Programming Interface 8Revision ID &  p.
0Ch8BIST 8Header Type 8Latency Timer 8Cache Line Size &  p.
10h 32 &
14h 32 &
18h 32 &
1Ch 32Base Address Register &
20h 32 &
24h 32 &
28h 32Cardbus CIS Pointer &
2Ch 16Subsystem ID 16Subsystem Vendor ID &
30h 32Expansion ROM Base Address &
34h 32Reserved &
38h 32Reserved &
3Ch8Max_Lat 8Min_Gnt 8Interrupt Pin8Interrupt Line &  p.
&31&&&&&&&24&23&&&&&&&16&15&&&&&&&8&7&&&&&&&0&
Type 00h configuration header space The second map presents the PCI-DDC specific registers:

&31&&&&&&&24&23&&&&&&&16&15&&&&&&&8&7&&&&&&&0&

40h24PCI-DDC Status8R3 Status &  p.
44h24PCI-DDC Status Mask8R3 Status Mask &  p.
48h32PCI-DDC Command &  p.
4Ch8Message Type24Received Message Identifier &  p.
50h32LPE Maximum Address &  p.
54h32LPE Current Address &  p.
58h32LPE New Address &  p.
5Ch32LPE Base Address &  p.
60h32LMI Maximum Address &  p.
64h32LMI Current Address &  p.
68h32LMI New Address &  p.
6Ch32LMI Base Address &  p.
70h32LRM Base Address &  p.
74h24Reserved8R3 Dout &  p.
&31&&&&&&&24&23&&&&&&&16&15&&&&&&&8&7&&&&&&&0&
PCI-DDC configuration space

Next: Device and Vendor Identification Up: Configuration registers Previous: Register access modes