Standard Status and Command Register

ASIM team
LIP6 Laboratory
Paris, France

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Standard Status and Command Register

Since PCI-DDC does not use all functionalities, most command bits are just readable.

22(R/C) Detected Parity Error 11(R) Fast Back-to-Back Enable
21(R/C) Signaled System Error 10(R/W) SERR# enable
20(R/C) Received Master Abort 9(R) Wait Cycle control
19(R/C) Received Target Abort 8(R/W) Parity Error Response
18(R) Signaled Target Abort 7(R) VGA Palette snoop
17(R) DEVSEL Timing 6(R) Memory Write
&15(R/C) Data Parity Error Detected 6and invalidate Enable
&14(R) Fast Back to Back Capable 5(R) Special Cycles
&13(R) UDF Supported 4(R/W) Bus Master
&12(R) 66 MHz Capable 3(R) Memory Space
&11 2(R) IO Space
&&&&&&&&&&&&
§-19.5pt &&&&&&&&&&&&
04h 10 10 10 10 10 20 0 10 10 10 10 5Reserved 6Reserved 10 10 10 10 10 10 10 10 10 10
&31&30&29&28&27&26&&24&23&22&21&20&&&&16&15&&&&&10&9&8&7&6&5&4&3&2&1&0&
16 Status 16 Command & Status and Command

Next: Status Up: Configuration registers Previous: Device and Vendor Identification