Serial macrocell

ASIM team
LIP6 Laboratory
Paris, France

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Serial macrocell

**Figure 7.2:** Serial Macrocell

Figure 7.2: Serial Macrocell
name I/O active level brief description

CKTX I - transmission clock

DIN[11:0] I 0xxxxxxxxxx1 parallel data to serialized

SDOUT O - outgoing serialized data

RESET I 1 macrocell reset

S_OP_EN I SDOUT forced to 0

CKR O - recovered clock

DOUT[11:0] O - deserialized data

SDIN I - incoming serial data

CAL O 1 deserializer is calibrated

**Figure 7.2:** Serial Macrocell
name	I/O	active level	brief description
CKTX	I	-	transmission clock
DIN[11:0]	I	0xxxxxxxxxx1	parallel data to serialized
SDOUT	O	-	outgoing serialized data
RESET	I	1	macrocell reset
S_OP_EN	I		SDOUT forced to 0
CKR	O	-	recovered clock
DOUT[11:0]	O	-	deserialized data
SDIN	I	-	incoming serial data
CAL	O	1	deserializer is calibrated

The calibration phase between two serial macrocells connected through a coax transmission line is divided into 2 steps.

When the signal RESET is released, the serializer starts calibrating. Since SDOUT is not well defined yet, it is set at 0 by maintaining S_OP_EN at 0. The calibration phase of the serializer lasts for about 2400 CKTX clock cycles. When S_OP_EN is set to 1, SDOUT is validated, the parallel data DIN is serialized.
The deserializer must received IDLE charactères for at least 3000 CKR clock cycles to be calibrated. When the deserializer is calibrated, the signal CAL gets high.

Synchronization between the two macrocells is maintained as long as the transmission is continued and the parallel data follow the condition din[0]=1 and din[11]=0.

Next: Boot Protocol Up: Serial link boot phase Previous: Serial link boot phase