Network Access

ASIM team
LIP6 Laboratory
Paris, France

Next: System Control and Status Up: SmartHSL Features Previous: PCI Access

Network Access

From the point of view of the DSP, the access to the HSL network is ensured by a pseudo register mapped in the DSP memory space. The datapath between the DSP and the router is 16 bit wide. Reading this register pops one 16 bit word from the incoming FIFO, writing it pushes one 16 bit word to the outgoing FIFO.

Datapath consists of two 512 word long FIFO (one for each direction). The status of these FIFO can be consulted via another register. This authorizes a flow control on a base of 1, 64, 256 words.

The DSP can be interrupted on the following events: reception register contains a data character, reception register contains a control character (e.g. End of Packet), transmission register is empty.

Next: System Control and Status Up: SmartHSL Features Previous: PCI Access