Performances

ASIM team
LIP6 Laboratory
Paris, France

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Performances

The PCI-DDC performances closely depends on the PCI bridge features and network load. Table 1 presents few evaluations based on reliable cycle precise simulation in a test bench including a complete PCI environment (memory, bridge, $\dots$ ) with PCI-DDC as unique peripheral device. For this simulation, the output and input RCUBE ports loop back in order that all outgoing packet immediately come back. This simulates a node with equal transmission and reception load.

$\begin{spacing} % latex2html id marker 61 {.8} \begin{table}[hbtp] \TimesX \capt... ...hroughput (Mb/s) & 4.7 & 80 & 124 \ \hline\end{tabular}\end{table}\end{spacing}$
All numbers in the top of the table are cycle numbers, which indicates when begins and ends the transaction. Column 1 gives an one-word message transfer latency from the first configuration write (step 2 on fig2) to the interrupt assertion once the LMI transaction is completed (step 7 on fig2). The RCUBE latency is 150ns. For 128 processors the largest distance between two processors is 7 hops. It means that the total hardware latency is less than 3 $\mu$ s. Column 2 and 3 gives results for longer messages. When the message length increases, the throughput increases close to the maximum PCI bus throughput, as shown in column 3.

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